CMS-FEE Emulator board

Emulator board

DESCRIPTION

The board is part of the CMS HCAL readout project.
Its purpose is to test the HTR demonstrator board and the DAQ integration (HRC+HTR+DCC).
It emulates the Hcal frontend electronics, the Trigger system and the LHC machine timing system.
It is a 6U VME slave.

It provides the following outputs:

signal level description

LHC_clock ecl Clock signal from the crystal oscillator (f_LHC= 40.0 MHz, T_LHC=25ns).
NB: The real LHC frequency is ~ 40.079... MHz. Future update of the crystal is possible.

ORBIT* ecl Active low signal obtained scaling the LHC clock by a factor of 3564 --> period = 88924ns; pulse width = 40 x T_LHC ~1us.
The position of the pulse is at the beginning of the gap, i.e. 3445 ticks from RX_BC0[1].

RX_clock[3..1] ttl copy of LHC_clock

RX_BC0[1] ttl The Bunch Crossing Zero is a 25 ns pulse synchronous with the first data (bunch # 0) of each orbit.
It is the time origin of the whole system (it is the internal BC0).
Period = 3564 x T_LHC ; width = T_LHC .

RX_BC0[3..2] ttl Copies of RX_BC0[1], delayed of a time = (18 + n)T_LHC, where n is individually adjustable via VME (8 steps required).

FE_Data[255..0] 8 fibers Frontend Data, several patterns should be available; mode selection from VME and on-board switches.
Duplex optical transmitters M2T-25-6-1-L from http://www.stratoslightwave.com

L1A* ecl L1Accept Trigger active low pulse; it should trigger on some of the FE_Data. Several trigger modes should be available, with mode selection from VME (e.g. trigger on all non-zero data, trigger on data above a threshold, trigger randomly at 100KHz).
The L1A* pulse has a delay of 127 T_LHC from the corresponding data.

All the signals are synchronous with the LHC clock. All the signals but the FE_Data are on lemo connectors.
Moreover one spare ttl I/O signal is provided on a lemo.

The signals emulating the LHC machine are:

LHC_clock (to TTCvx)
ORBIT* (to TTCvi)

The signals emulating the Front-End electronics are

FE_Data[255..0] (8 fibers to 2 HTR demo boards)

The FE_Data follow the LHC structure, that is data are zero in the gaps
(main gap inplemented from the beginning, secondary gap implemented
in future).

The signal emulating the Global Trigger is:

L1A* (to TTCvi)

The RX_clock and RX_BC0 will eventually be generated in the readout crate
by HRC or an independent fanout module under development at UIC.

The main components are two Altera EPF10k50E (41 kbit of RAM each)
Each Altera drives 4 fibers (i.e. 8 detector channels).
The G-link transmitters are HDMP1032.
A generic VME address map and registers has been defined, as a reference for
FPGA design and VME software coding. The features presently implemented are
defined on the links at the bottom of the page.

Layer organization and power planes:

Top: components + routing + local GND plane under 2 HDMP1032 (thank to an idea of Erik van der Bij )
L2 : 3.3A plane cut (for VCCA of HDMP1032) + routing
L3 : routing
L4 : mixed digital power plane : 5V, 3.3V, 2.5V
L5 : GND
L6 : smd + routing
Bottom: smd + routing

PDF files :

Schematic files
Schematic - page 1 (electrical I/Os, etc)
Schematic - page 2 (G-Link transmitters)
Schematic - page 3 (G-Link transmitters)

Lay-out files
Top layer placement
Top layer P&R
Bottom layer placement
Bottom layer P&R
Layer 4
Layer 2

Pin assignements
Top FPGA by pin number
Top FPGA by signal names
Bottom FPGA by pin number
Bottom FPGA by signal names

STATUS

Submission: 12 December 2000   (Number of printed boards: 5)
Starting of FPGA design: FEB 2001
Starting of testings : 1 MAR 2001
G-Link working (FEemul sending to HTRdemo) : end of MAR 2001
         G-Link settings at 800 Mb/s: DIV1=0, DIV0=1, ESMPXENB=0, FLAGENB=x, TCLKENB=0 (PASSENB = 0 on HTR).
         Removed ground terminations: R1,R2,R3,R4,R5,R7,R9,R10,R12,R13,R14,R15,R16,R17,R18,R19.
VME Test Control Code by Aaron McQueen : MAY 2001
FPGA Design version 1 by Hans Breden : 13 JUNE 2001

Tullio Grassi - 25 JUNE 2001
Return to my HCAL CMS working page

signal	level	description
LHC_clock	ecl	Clock signal from the crystal oscillator (f_LHC= 40.0 MHz, T_LHC=25ns). NB: The real LHC frequency is ~ 40.079... MHz. Future update of the crystal is possible.
ORBIT*	ecl	Active low signal obtained scaling the LHC clock by a factor of 3564 --> period = 88924ns; pulse width = 40 x T_LHC ~1us. The position of the pulse is at the beginning of the gap, i.e. 3445 ticks from RX_BC0[1].
RX_clock[3..1]	ttl	copy of LHC_clock
RX_BC0[1]	ttl	The Bunch Crossing Zero is a 25 ns pulse synchronous with the first data (bunch # 0) of each orbit. It is the time origin of the whole system (it is the internal BC0). Period = 3564 x T_LHC ; width = T_LHC .
RX_BC0[3..2]	ttl	Copies of RX_BC0[1], delayed of a time = (18 + n)T_LHC, where n is individually adjustable via VME (8 steps required).
FE_Data[255..0]	8 fibers	Frontend Data, several patterns should be available; mode selection from VME and on-board switches. Duplex optical transmitters M2T-25-6-1-L from http://www.stratoslightwave.com
L1A*	ecl	L1Accept Trigger active low pulse; it should trigger on some of the FE_Data. Several trigger modes should be available, with mode selection from VME (e.g. trigger on all non-zero data, trigger on data above a threshold, trigger randomly at 100KHz). The L1A* pulse has a delay of 127 T_LHC from the corresponding data.