| Dir | N. | signal | notes |
| IN | 4 | FE_Data[63:0] | G-link optical fibers from FEE; Dual LC connector : M2R-25-6-1-TL from http://www.stratoslightwave.com |
| IN | 1 | TTC fiber | through TTCrx test daughter card |
| IN | 1 | optional external clock | ttl lemo |
| IN | 1 | test trigger | ttl lemo, reconfigurable for different use |
| IN | 1 | RX_CLK | common clock for TPG SYNC |
| IN | 1 | RX_BC0 | common bc0 for TPG SYNC |
| I/O | 1 | JTAG port | chain: Apex, SYNC, TTCrx board, Link board |
| I/O | VME J1 and J2 | 5-row VME connector. A jumper select 3.3V from VME or V_reg | |
| OUT | 2 | 24-bit TPG data | on 2 PMC-syle connectors |
| OUT | 1 | 5-pair Channel Link | L2-DAQ data to DCC (28-bit at 40 MHz) |
| OUT | 1 | clock | ttl lemo |
| OUT | 1 | test trigger | ecl lemo, reconfigurable |
The main component is an Altera APEX EP20k400BC652-1V (213kbit of RAM)
The G-link receivers are HDMP1034.
The Channel Link transmitter is a DS90CR285
The TPG SYNC chip (from CMS-ECAL) is an Altera ACEX EP1k50.
Layer organization:
Top: components + routing + local GND plane under
two HDMP1034 (thank
to an idea of Erik van der Bij )
L2 : GND
L3 : routing
L4 : +2.5V (core of Apex)
L5 : routing
L6 : +5V
L7 : +3.3V
Bottom: smd + routing
PDF files :
Schematic files
page
1 (Apex)
page
2 (VME, voltage regulators, etc)
page
3 (I/Os and G-Link receivers)
page
4 (SyncTx/Rx FPGA and Link Piggy Board)
page
5 (BGA duplicate, for access to Apex pins on the bottom layer)
Lay-out files
Top layer placement
Top layer P&R
Bottom layer placement
Bottom layer P&R
Pin assignement of the fpga:
sorted by pin number
sorted by signal names
STATUS
Submission:
12 December 2000
Number of printed boards:
7
Starting of fpga design:
December 2000
Starting of testings:
1 March 2001
G-Link working (FEemul sending to HTRdemo) : end of MAR
2001
G-Link settings at 800 Mb/s:
DIV1=0, DIV0=1, ESMPXENB=0, FLAGENB=x, PASSENB = 0.
FPGA
design version 0.0 :
28 MAY 2001
Two more boards stuffed and tested with design version
0: June 2001
Two boards sent to BU and FNAL:
28 JUNE 2001
FPGA
design version 0.1 :
8 JULY 2001
FPGA
design version 0.2 :
24 AUG 2001
FPGA
design version 0.5 :
31 OCT 2001 [version succefully tested in BU]
Tullio Grassi - 31 Oct 2001
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