Top view of HTR block diagrams

    Input stage
        Clock synchronization
        Delay adjustment
    CapID error

    L1 path
        L1 LUT
        Energy sum
        L1 Filter
            L1 Energy FIR
            BCID peak-finder
        Muon window
        E_T & compression
        TP format
        Synchronization and serial link

    L2 path
        DAQ data
        Trigger Primitives data
        Pipeline
        Derandomizer
        Communication HTR->DCC
 

 Tullio Grassi - 30 Jan 2001.